中国科大微电子学院
  

朱慧珑

邮箱:zhuhuilong@ime.ac.cn

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经历:
1982-09--1988-07 北京师范大学 理学物理博士
1978-03--1982-07 中国科学技术大学 理学学士

简介:

超大规模集成电路的研究,现担任“22纳米关键工艺技术先导研究与平台建设”课题首席专家, 该项目属国家科技重大专项“极大规模集成电路制造装备及成套工艺”.中国科学院微电子研究所研究员,博士生导师。提出了多项提高芯片性能的核心技术方案,其中包括双应力薄膜(Dual Stress Liner)、应力近临技术(stress proximity technique)、减薄栅极的应变MOSFET等; · 较系统地研究了锗和锑在SixGe1-x体系中的扩散现象,提出了新的数学模型及解析解法,并第一次给出了精确描述锗和锑在SixGe1-x体系中扩散系数的公式。


荣誉:
- IBM全公司2007年度4名引领发明家(Leading Inventor)之一;
- IBM半导体研究和开发中心2008年度的发明大师(Master Inventor);
- 2项专利获IBM杰出专利奖;
- 获得IBM公司发明成就奖51次.。


论文:

1) H. Zhu et al, “Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner,” VLSI 2007, pp180-181

2) H. Zhu et al, “On the Control of Short Channel Effect for MOSFETs with Reverse Halo Implantation” IEEE Electron Device Lett., vol. 28, no. 2, pp168-170, 2007。

3)H. Zhu, “Modeling of Impurity Diffusion with Vacancy-Mechanism in Diamond Lattice and Si1-xGex,” Electrochemical Society Proceedings Volume 2004-07, pp. 923-934

4) H. Zhu et al, “STRUCTURE AND METHOD TO ENHANCE STRESS IN A CHANNEL OF CMOS DEVICES USING A THIN GATE”, US Patent application number: US20060160317A1

5) H. Zhu et al, “Structure and method for manufacturing planar SOI substrate with multiple orientations”, US Patent number: US7094634.

6) H.S. Yang and H. Zhu, “Method and Apparatus for Increase Strained Effect in a Transistor Channel,” US Patents: US7118999 and US7462915

7) K. Lee and H. Zhu, “Method for slowing down dopant-enhanced diffusion in substrates and devices fabricated therefrom,” US Patent: US7163867

8) B. Doris et al, “Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers” US Patent Application: US20050093030A1

9) H. Zhu and R. S. Averback, Sintering processes of two nanoparticles: a study by molecular-dynamics simulations, Phil. Mag. Lett. 73, no.1, (1996): 27-33.

10) H. Zhu et al, “Molecular-Dynamics Simulations of a 10-keV Cascade in Beta-NiAl,” Philosophical Magazine A71 735-758, 1995


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